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Espressif Systems /ESP32-C3 /SPI2 /USER

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Interpret as USER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DOUTDIN)DOUTDIN 0 (QPI_MODE)QPI_MODE 0 (TSCK_I_EDGE)TSCK_I_EDGE 0 (CS_HOLD)CS_HOLD 0 (CS_SETUP)CS_SETUP 0 (RSCK_I_EDGE)RSCK_I_EDGE 0 (CK_OUT_EDGE)CK_OUT_EDGE 0 (FWRITE_DUAL)FWRITE_DUAL 0 (FWRITE_QUAD)FWRITE_QUAD 0 (USR_CONF_NXT)USR_CONF_NXT 0 (SIO)SIO 0 (USR_MISO_HIGHPART)USR_MISO_HIGHPART 0 (USR_MOSI_HIGHPART)USR_MOSI_HIGHPART 0 (USR_DUMMY_IDLE)USR_DUMMY_IDLE 0 (USR_MOSI)USR_MOSI 0 (USR_MISO)USR_MISO 0 (USR_DUMMY)USR_DUMMY 0 (USR_ADDR)USR_ADDR 0 (USR_COMMAND)USR_COMMAND

Description

SPI USER control register

Fields

DOUTDIN

Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
QPI_MODE

Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
TSCK_I_EDGE

In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
CS_HOLD

spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
CS_SETUP

spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
RSCK_I_EDGE

In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
CK_OUT_EDGE

the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
FWRITE_DUAL

In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
FWRITE_QUAD

In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
USR_CONF_NXT

1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
SIO

Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
USR_MISO_HIGHPART

read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
USR_MOSI_HIGHPART

write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
USR_DUMMY_IDLE

spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
USR_MOSI

This bit enable the write-data phase of an operation. Can be configured in CONF state.
USR_MISO

This bit enable the read-data phase of an operation. Can be configured in CONF state.
USR_DUMMY

This bit enable the dummy phase of an operation. Can be configured in CONF state.
USR_ADDR

This bit enable the address phase of an operation. Can be configured in CONF state.
USR_COMMAND

This bit enable the command phase of an operation. Can be configured in CONF state.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data